System Level Verification and Performance Analysis for FPGA Accelerated Computers

System Level Verification and Performance Analysis for FPGA Accelerated Computers Zhimin Chen, Xu Guo, Ambuj Sinha, and Patrick Schaumont Department of Electrical and Computer Engineering Virginia Tech, Blacksburg, VA 24060, USA E-mail: {chenzm, xuguo, ambujs87, schaum}@vt.edu. As an accelerator, Field Programmable Gate Array (FPGA) has become a great potential to assist a general-purpose processor in performance-critical tasks. A common integration approach is to configure the FPGA as a slave device to the general-purpose processor. In this case, the FPGA implements the equivalent of a function call in hardware for the general-purpose processor. For a given application, a designer will then identify the performance-critical part, and implement that part as a hardware unit onto the FPGA fabric. As the FPGA capacity increases, designers can replicate such a unit in one FPGA and obtain a multi-core system. The generalpurpose processor will take care of data-handling (operands and results) for the FPGA, and it will maintain system-control for the overall application. While this accelerator scenario is easy to understand, it creates two important challenges for designers. One challenge is the systemlevel verification in order to obtain a quick edit/compile/debug cycle. The second challenge is performance analysis in a computing paradigm that mixes traditional computer architecture and FPGAbased processing. In this contribution, we share our experiences in system level verification with hardware-software codesign. We also present our method to identify the system bottlenecks and further to analyze the system performance. FPGAs are programmed using Hardware Description Languages (HDL), and instruction-set processors are programmed in a sequential programming language. In the accelerator scenario described above, the hardware design paradigm, common to FPGA programming, must be integrated into the software design paradigm, used by instruction set processors. In this contribution, we consider the use of hardwaresoftware codesign for this issue. We combine RTL design on the FPGA with software programming on the general-purpose processor. This gives us precise control over the part of the application mapped into hardware, and over the design of the hardware-software interface between the FPGA and the general-purpose processor. While it is always possible to use a compile-and-see-what-happens approach to FPGA accelerator design, this approach becomes inefficient for high-end FPGA designs, because the design compilation time is too high. Furthermore, the observability of a design on an FPGA is low, and requires specialized debugging infrastructure. We propose a solution, called host-based cosimulation, that cosimulates the application on the host processor with the RTL design of the accelerator. Host-based cosimulation is capable to verify the RTL without going through the design compilation and to debug only based simulation. Besides system level verification, we also address the performance analysis challenge. We find that such a system, in which the FPGA executes as a slave device, may exhibit three different bottlenecks, which can be attributed to computational limits, communicationbandwidth limits, and storage limits, respectively. We identify five design factors that play critical roles on deciding the system performance, including the number of parallel units that can be implemented in an FPGA, the size of data sent to each unit in each N o r t h